AMD announced its Versal tamper-resistant, or TR, devices on November 13, a new family of adaptive processors built to protect security-critical information against sophisticated physical attacks. Based on the Versal AI Edge Series Gen 2 platform, the devices are aimed at organizations that handle sensitive information in defense systems, critical industrial infrastructure, data center networking and financial technology.
AMD says the Versal TR devices are the first adaptive SoC or FPGA-based devices to provide built-in protection against physical attacks on the silicon backside, a claim the company bases on its own internal analysis from November 2026 comparing anti-tamper and standard security features in competing products. At the center of the design is a sensor-based protection die bonded to the main compute die using 3D active-on-active technology. That protection die shields the entire backside of the device, detects physical attacks, and prevents the device from booting if the protection die is tampered with or removed.
The pitch is aimed at a costly status quo. Customers who need this level of protection today typically build custom solutions in-house using mechanical enclosures, ASICs and other components, which AMD says adds development cost, specialist resources, verification effort and re-spin risk. By combining compute, security and enclosure-style protection in a single device, the company says Versal TR can save board area and simplify board design while keeping customers on AMD tools and its partner ecosystem. AMD is careful to note that tamper-resistant does not mean tamper-proof, and that protection applies only to specified physical attack methods described in the product documentation.
Protection against physical attacks is only part of the package. The devices expand hardware acceleration for post-quantum cryptography, adding new support for the Module-Lattice-Based Digital Signature Algorithm, known as ML-DSA, and the Stateless Hash-Based Digital Signature Algorithm, known as SLH-DSA. They also support a hybrid boot flow that lets users leverage multiple signature algorithms, add improvements to the application security unit key vault, and include a new memory element aging sensor to provide additional safeguards for cryptographic keys. Glitch detection has been expanded as well, combining improvements to the existing Versal architecture glitch detector with a new orthogonal glitch detector that covers glitches occurring simultaneously across two voltage rails.
On performance, the devices integrate Arm CPUs, AI Engines, programmable logic, hard IP and connectivity, delivering up to 229,000 DMIPS of scalar compute, up to 369 INT8 TOPS of AI processing throughput and up to 543,000 LUTs of programmable logic. The portfolio includes three devices, the 2VE3358TR, 2VE3558TR and 2VE3858TR, spanning different performance tiers and cost points on a common platform.
There is a practical on-ramp for designers who cannot wait. Each Versal TR device has a footprint-compatible standard counterpart available today, so customers can develop on the standard Versal AI Edge Series Gen 2 platform now and transition to the tamper-resistant device later without rerunning synthesis or place and route. The first Versal TR devices are expected to sample in the second half of 2027 and move to production in the first half of 2028, giving security-focused teams a long, clearly signaled runway to build designs that can adopt the stronger hardware protection when it arrives.